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本文旨在帮助学生初步了解华为τ定律，提前熟悉高考英语阅读理解相关的话题。
A Time Scaling Theory for Multi-Layer Electronic Systems
多层电子系统的时间缩放理论
Abstract：
For six decades, Moore's geometric scaling drove progress in semiconductors. That industry compact no longer holds: returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling. This perspective argues for a successor scaling principle — τ scaling — that adopts time itself, rather than transistor area, as the primary metric of progress, applying a single characteristic time constant τ as the unifying optimization target across twelve orders of magnitude, from a switching transistor to a data-center workload. Two production-scale demonstrations are presented. On a mobile SoC, LogicFolding — a methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers — delivers a 55% step-wise increase in transistor density and a 41% power-efficiency gain at a fixed device node. On AI systems, a co-designed stack comprising the memory-semantic Unified Bus fabric, near-packaged Hi-ONE optical I/O, and edge-to-surface 3D Folding projects more than 100x growth in hardware integration by 2035. The deeper claim（看法；主张） is methodological / meθ. .d lɑ .d .k l/: τ scaling is the first scaling principle since Dennard to establish a shared optimization target across the entire computing stack.
Keywords: Time Scaling, τ scaling, LogicFolding, Semiconductor, Electronic systems, New semiconductor path
摘要：
六十年来，摩尔定律的几何缩放一直驱动着半导体领域的进步。但这一产业契约已不再适用：单纯靠缩小尺寸带来的收益已经趋缓，尖端芯片的设计预算超过每颗十亿美元，而在最先进的工艺节点上，单位晶体管成本已不再下降。本文提出一种接续性的缩放原理——τ缩放——它将时间本身，而非晶体管面积，作为衡量进步的首要指标，并以单一特征时间常数 τ 作为跨十二个数量级（10 倍）的统一优化目标，覆盖从单个开关晶体管到数据中心工作负载的整个范围。文中展示了两个达到量产规模的实例。在一款移动 SoC 上，LogicFolding（一种将数字、模拟和存储电路划分到垂直堆叠有源层中的方法）在固定器件节点下实现了晶体管密度阶跃式提升 55%，能效提升 41%。在 AI 系统方面，通过协同设计的存算语义统一总线架构、近封装 Hi-ONE 光学 I/O 以及边缘到表面的 3D Folding 技术，预计到 2035 年硬件集成度将增长超过 100 倍。更深层的贡献在于方法论：τ缩放是继 Dennard 缩放之后，第一个为整个计算栈建立统一优化目标的缩放原理。

关键词：
时间缩放；τ缩放；LogicFolding；半导体；电子系统；半导体新路径

A Time Scaling Theory for Multi-Layer Electronic Systems

补充注释：
1). demonstrations “实例”或“演示验证”，在学术摘要中通常指具体的技术方案或系统实现案例。

2).“twelve orders of magnitude” 指的是 10 倍（即 1,000,000,000,000 倍，一万亿倍） 的范围。在科学和工程中，“一个数量级”就是 10 倍，所以 12 个数量级意味着最小值和最大值之间相差 10 倍。
在这篇论文的语境中，作者说 τ（特征时间常数）要作为一个统一的优化目标，跨越从单个晶体管的开关时间到数据中心完整工作负载的执行时间。举例来说：
一个晶体管的开关时间大约是 纳秒（10 秒） 级别。

一个数据中心的任务（例如训练一个 AI 模型或处理一个大查询）可能耗时 数百秒甚至上千秒，比如 10 秒。
从 10 秒到 10 秒，正好相差 10 倍，也就是 12 个数量级。
所以这句话强调：τ 缩放理论能够用同一个时间常数 τ 来指导从最底层器件到最高层系统（横跨万亿倍的时间尺度）的优化设计，这是非常宏大且统一的思想。
3).active tiers：“有源层” 或 “有源器件层”。
这里 “active” 指的是包含晶体管等有源器件的层（相对于仅含金属布线或绝缘介质的无源层）。在三维集成技术中，垂直堆叠多个有源器件层（例如将逻辑电路、模拟电路、存储电路分别制作在不同层上，再通过过孔互连）正是 LogicFolding 的核心思想。
.device node:在半导体领域，device node（器件节点）通常就是指工艺节点（technology node），例如 7nm、5nm、3nm 等。它代表了集成电路制造工艺中晶体管的关键尺寸（如栅极长度、半节距等）所达到的水平。
、a fixed device node:固定工艺节点，即不改变基础工艺节点（比如仍然使用 5nm 工艺），仅仅通过 LogicFolding 这种三维堆叠设计方法，就实现了晶体管密度和能效的大幅提升。这强调了方法本身带来的收益，而不是依赖进一步缩小器件尺寸（摩尔定律的旧路径）。
、co-designed stack：协同设计的技术栈（指软硬件协同、多层级联合设计的技术体系）→ the entire computing stack 整个计算栈
、memory-semantic Unified Bus fabric：存算语义的统一总线架构（强调总线不仅传输数据，还理解内存语义）
8)、near-packaged Hi-ONE optical I/O：近封装 Hi-ONE 光学 I/O（光学输入输出接口，靠近芯片封装集成）
9)、edge-to-surface 3D Folding：边缘到表面的 3D Folding（一种三维集成技术，从芯片边缘到表面进行折叠式堆叠）
10)、Harness Engineering（驾驭工程） 是AI智能体（Agent）的核心支撑体系，如果将基础的大模型比作一匹动力无限但难以掌控的“野马”，那么Harness就是那套精密的 “马具” （缰绳、马鞍、护栏），它既能让马匹尽情发挥动力，又能确保骑手能有效驾驭，使其成为一匹稳定可靠的“赛马”。
核心公式：AI 智能体 (Agent) = 大模型 (Model) + Harness。这个公式深刻地揭示了模型能力与工程系统对于构建可靠AI缺一不可的关系。也就是说，Harness Engineering 是AI智能体（Agent）的核心支撑体系，本质可概括为：Agent = LLM + Harness。它并非优化提示词或升级模型，而是通过构建运行环境、任务机制与规则边界，将大模型能力转化为可落地的生产工具，实现AI智能的工程化实践。
Read the following essay and then answer the comprehension questions below.
A Time Scaling Theory for Multi-Layer Electronic Systems
For the past sixty years, Moore's Law (the idea that transistor size shrinks every two years) drove progress in computer chips. But that rule no longer works: simply making transistors smaller brings little benefit, designing the most advanced chips now costs over one billion dollars each, and the cost per transistor is no longer falling.
This paper proposes a new scaling rule — τ scaling (τ, pronounced "tau", is a symbol for a characteristic time constant). Instead of focusing on transistor area, this rule uses time as the main measure of progress. A single time constant τ becomes the common optimization goal for everything from a single switching transistor to a whole data-center workload — across a range of 10 (a million million times).
We show two real-world, large-scale demonstrations:
On a mobile SoC (System on a Chip, the main chip in a phone), a method called LogicFolding spreads digital, analog, and memory circuits across vertically stacked active layers (like stacking floors in a building). At the same device node (same manufacturing technology), this achieves a 55% increase in transistor density and a 41% gain in power efficiency.
For AI systems, a co-designed set of technologies — including the Unified Bus (a memory-semantic communication fabric), Hi-ONE optical I/O (a very fast optical connection placed near the chip package), and edge-to-surface 3D Folding — is projected to increase hardware integration by more than 100 times by 2035.
The deeper claim is about methodology (the approach itself): τ scaling is the first scaling principle since Dennard scaling (an earlier rule from the 1970s) that sets a shared optimization target across the entire computing stack — from transistors to software.
1. What specific improvements did LogicFolding bring to a mobile SoC at the same device node
A. 41% higher transistor density and 55% better power efficiency.
B. 55% higher transistor density and 41% better power efficiency.
C. 100 times higher integration and lower cost per transistor.
D. A reduction in design cost to under one billion dollars.
2. According to the passage, what is the projected outcome of the co designed technologies for AI systems by 2035
A. They will replace Dennard scaling completely.
B. They will reduce the time constant τ to zero.
C. They will increase hardware integration by more than 100 times.
D. They will make Moore's Law work again.
3. The underlined word “methodology” in the last paragraph most likely means ______.
A. a set of scientific equipment
B. a system of methods or principles used in a particular field
C. a type of computer chip architecture
D. a historical rule from the 1970s
4. What is the main purpose of the passage
A. To prove that Moore's Law has completely failed and must be abandoned.
B. To introduce a new time based scaling theory and support it with experimental results.
C. To compare the manufacturing costs of mobile SoCs and AI systems.
D. To explain how to stack active layers vertically in chip design.
Answers & Explanations:
1. B – 细节题1。根据文章第三段：“At the same device node… this achieves a 55% increase in transistor density and a 41% gain in power efficiency。”注意选项A颠倒了数字，C项100倍是针对AI系统的预测，D项未提及。
2. C – 细节题2。根据文章第四段：“…is projected to increase hardware integration by more than 100 times by 2035。”A项“取代Dennard缩放”无依据；B项“τ变为零”错误；D项“让摩尔定律重新生效”未提及。
B – 词义猜测题。文中最后一句：“The deeper claim is about methodology: τ scaling is the first scaling principle since Dennard scaling that sets a shared optimization target…” 结合上下文，“methodology”指的是τ缩放作为一种研究或设计的方法体系，即“一套方法或原则”。A项“科学设备”、C项“芯片架构”、D项“1970年代的历史规则”均不符合语境。
B – 主旨大意题。文章第一段指出摩尔定律失效，第二段提出新的τ缩放理论（以时间为核心），第三、四段给出两个实际验证案例（手机SoC和AI系统），最后一段强调该方法论的意义。因此主要目的是介绍基于时间的缩放理论并提供实验证据。A项“完全失败且必须抛弃”过于绝对；C项比较成本非主旨；D项只涉及一个技术细节。
语法填空（共10小题；每小题1.5分，满分15分）
阅读下面短文，在空白处填入1个适当的单词或括号内单词的正确形式。
A Time Scaling Theory for Multi-Layer Electronic Systems (adapted)
For the past sixty years, Moore's Law — the idea 1. ______ transistor size shrinks every two years — 2. ______ (drive) progress in computer chips. But that rule no longer 3. ______ (work): simply making transistors smaller brings little benefit, 4. ______ (design) the most advanced chips now costs over one billion dollars each, and the cost per transistor is no longer falling.
This paper proposes a new scaling rule 5. ______ (call) τ scaling. Instead of focusing on transistor area, this rule uses time as the main measure of progress. A single time constant τ becomes the common optimization goal for everything from a single switching transistor to a whole data-center workload — across 6. ______ range of 10 .
We show two real-world demonstrations. On a mobile SoC, a method 7. ______ (name) LogicFolding spreads digital, analog, and memory circuits across vertically stacked active layers, 8. ______ (achieve) a 55% increase in transistor density and a 41% gain in power efficiency. For AI systems, a co-designed set of technologies is projected 9. ______ (increase) hardware integration by more than 100 times by 2035. The deeper claim is about methodology: τ scaling is the first scaling principle since Dennard scaling 10. ______ sets a shared optimization target across the entire computing stack.
参考答案与解析
题号 答案 考点 解析
1 that 连词（同位语从句） 引导同位语从句，说明 idea 的具体内容，从句结构完整，用 that。
2 has driven 动词时态（现在完成时） “for the past sixty years” 常与现在完成时连用，表示从过去持续到现在的动作。
3 work 情态动词 + 动词原形 no longer 后面接动词原形，work 意为“起作用、奏效”。
4 designing 非谓语动词（动名词作主语） 动名词短语 “designing the most advanced chips” 作主语，谓语动词用 costs。
5 called 非谓语动词（过去分词作定语） “a new scaling rule called τ scaling” 意为“被称为 τ 缩放的新规则”。
6 a 冠词（固定搭配） “across a range of…” 是固定搭配，意为“在…范围内”。
7 named 非谓语动词（过去分词作定语） “a method named LogicFolding” 意为“一种名为 LogicFolding 的方法”。
8 achieving 非谓语动词（现在分词作结果状语） 现在分词短语表示自然而然的结果，意为“从而实现了…”。
9 to increase 非谓语动词（不定式） “be projected to do sth.” 是固定搭配，意为“预计会做某事”。
10 that / which 连词（定语从句关系代词） 引导定语从句修饰先行词 principle，在从句中作主语，可用 that 或 which。
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